Sense amplifiers are one of the most critical circuits in a periphery of memory devices. They are used to sense data information from an array of cells in a memory device. The sense amplifier's performance strongly affects both memory access time and overall function of the memory device. As with other integrated circuits, memory devices are required to become increasingly faster. Sense amplifiers are also required to become commensurately faster.
The sense amplifier detects a high or a low data value, differing by a small voltage, presents the value found in a proper level for a correct logic level representation outside the memory, and is quickly ready to repeat this read process for the next memory location. To do this, a sense amplifier must be able to detect a difference between a high and a low level in a storage element that may be several hundred millivolts. The sense amplifier must correctly detect small voltage differences without excessive depletion or injection of charge in the storage element being sensed so that the correct level is maintained in storage and successive read operations are started rapidly. The sense amplifier must be able to provide a large enough voltage level representation to the consuming logic for a proper result. The sense amplifier must supply this result with a small propagation delay to maintain quick memory access and high throughput. To provide high throughput, the memory device must be able to cycle quickly through these requirements each time a new memory location is read.
An input node of a sense amplifier is typically connected directly to a bit-line of a memory array, which may contain many memory cells. A total capacitance loading on the bit-line is very large. Such large capacitances result in slow input slew rates and increased signal propagation delay. Various circuit techniques have been used to reduce the signal swing on the bit-lines to achieve high-speed operation. These techniques commonly require a large DC bias current through the amplifying stages and thus are not suitable for applications requiring low stand-by DC current, which is the case in products such as battery operated consumer electronics applications. To reduce the overall energy consumed by a memory device, sense amplifiers can be conditionally turned on briefly when a content of a memory bit needs to be read out, remaining turned off otherwise, consuming zero DC current. This defines a low current operation mode, commonly referred to as Low Power Mode. Different design techniques, such as edge detection circuits, can be used to determine when to turn on the sense amplifiers. Usually, when the sense amplifier is turned off, the input node and the output node are coupled together to form a latch. This preserves the information from the last memory access. The formation of the latch places the input node at full CMOS levels. If the input node of the sense amplifier is directly coupled to the memory bit-line, which has heavy capacitive loading, the memory bit-line will also be forced to a full CMOS level. Upon subsequent memory accesses, if the content of a memory cell presents a different logic value than the previously accessed memory bit, a large voltage swing is seen on the bit-line before the sense amplifier can detect a correct logic level. This voltage swing is much larger than the voltage swing on the bit-line during normal sense amplifier operation. This larger voltage swing results in much larger propagation delays.
A prior art circuit technique isolates the heavily loaded bit-line from the sense amplifier input node during latching in Low Power Mode and only latches the sense amplifier input node to a CMOS level. This technique reduces the voltage swing seen on the bit-line when the sense amplifier wakes up. It can significantly reduce the Low Power Mode propagation delay. However, a charge-sharing path exists between the sense amplifier input node and bit-line in the prior art technique. Under certain conditions, the charge sharing path pumps up the bit-line voltage to a level significantly higher than its normal mode bias level and introduces significantly larger signal swing on the bit-line when the sense amplifier wakes up. As a consequence of a larger signal swing, the Low Power Mode signal propagation delay increases significantly. This delay decreases the effectiveness of the bit-line isolation technique.
FIGS. 1–4 illustrate an overview of a prior art sense amplifier having delay problems in the logic low signals.
With respect to FIG. 1, an exemplary embodiment of a schematic diagram of a sense amplifier 100, representative of the prior art, is shown. A memory cell 151 consists of a storage transistor 160 and a select transistor 155 connected in series. A memory cell array 165 is composed of many memory cells 151 with each select transistor 155 controlled by a separate word line 152. The memory cells 151 are connected in parallel to a bit-line 170. The bit-line 170 is connected to a sense amplifier input, sa_in 140, through a first NMOS transistor 150. The first NMOS transistor 150 is configured with a source connection to the bit-line 170, a drain connection to the sense amplifier input sa_in 140, and a gate connection to a signal Pd_lat# 115. The sense amplifier input, sa_in 140, connects to a first of four inverters 130 connected in series with the fourth inverter having an output connection to the output terminal sa_out 135. The output of the first inverter of four inverters 130 is connected to an input gate of a second NMOS transistor 125 with a source connection to sa_in 140 and a drain connection to the drain of a pull-up PMOS transistor 112. The second NMOS transistor provides feedback to the input of the sense amplifier 100 for level sensing. The source of the pull-up PMOS transistor 112 is connected to Vcc. The gate of the pull-up PMOS transistor 112 is connected to an input Pd 110 An output of the fourth inverter 130 is connected to the input of a transmission gate 138. An output of the transmission gate 138 forms a latching path when connected to sa_in 140. Pd_lat# 115 and a signal Pd_lat 120 control the latching path.
With reference to FIG. 2, a detailed schematic diagram of a sense amplifier 200 is illustrated. The sense amplifier 200 comprises a biasing circuit 202, a first inverter 220, a second inverter 240, a third inverter 260, a feedback latching path 280, and a bit-line path 290.
The biasing circuit 202 sets the bias voltage level on sa_in 140 in high power mode for the sense amplifier 200 and comprises a PMOS pull-up transistor 204 coupled in series to an NMOS transistor 206. A first input terminal (Pd) 210 is coupled to the gate of the PMOS pull-up transistor 204. The source of the PMOS pull-up transistor 204 is coupled to a power supply 212. The gate of the NMOS transistor 206 is coupled to an output terminal of the first inverter 220 in form of a feedback.
The first inverter 220 is, for example, a typical CMOS inverter with two pull-up PMOS transistors and a pull-down NMOS transistor. An input of the first inverter 220 is coupled to the bit-line path 290. An output of the first inverter 220 is coupled to an input of the second inverter 240 to form a buffer. As mentioned earlier, the output of the first inverter 220 is also coupled to an input (or the gate of the NMOS transistor 206) of the biasing circuit 202 to form a feedback therewith.
The second inverter 240 and the third inverter 260 are, for example, a typical CMOS inverter with a PMOS pull-up and an NMOS pull-down transistor. The output of the fourth inverter 265 forms an output terminal 286 (sa_out) of the sense amplifier 200.
The feedback latching path 280 is, for example, a transmission gate forming a latching path which is well-known to a person of ordinary skill in the art with a PMOS transistor and an NMOS transistor coupled together in parallel. Their sources are coupled together and to the output terminal 286, their drains are coupled together and to the bit-line path 290.
The bit-line path 290 has three input terminals, an NMOS switch 298, and a parasitic capacitor 292 associated with sa_in 295. The three input terminals are a second input terminal 294 (Pd_lat#), a third input terminal 296 (bitln), and sa_in 295. The drain of the NMOS switch 298 is coupled to the third input terminal 296 (bitln). The source of the NMOS switch 298 is coupled to the input terminal of the first inverter 220, to the drain of the feedback latching path 280, and to the source of the NMOS pull-down transistor 206 of the biasing circuit 202 to form the input sa_in 295 for the sense amplifier 200.
With further reference to FIG. 2, the modes of the sense amplifier 200 are determined by the following three input signals: the first input terminal (Pd) 210, the second input signal (Pd_lat#) 294, and the fourth input signal (Pd_lat) 299. These are control signals. In a high power mode, the first input signal (Pd) 210 stays LOW, the second input signal (Pd_lat#) 294 stays HIGH, and the fourth input signal (Pd_lat) 299 stays LOW. As a result, the PMOS pull-up transistor 204 is ON, raising the input sa_in 295 of the sense amplifier 200 to a bias voltage level. When the second input terminal 294 (Pd_lat#) is HIGH and the fourth input signal 299 is LOW, the feedback latching path 280 is OFF because its PMOS transistor and NMOS transistor are both OFF. Thus, the feedback latching path 280 isolates the output terminal 286 (sa_out) from the third input terminal 296 (bitln) of the sense amplifier 200.
In the high power mode, the voltage of the third input terminal 296 (bitln) varies from a logic LOW bias voltage (Vbias—Lo) to a logic HIGH bias voltage (Vbias—HIGH) to turn the inverters 220, 240, 260, and 265 ON or OFF respectively. Typically, the voltage swing between Vbias—LOW and Vbias—HIGH is about 200 mV. Under this condition, the third input terminal 296 (bitln) causes the NMOS switch 298 to bias at the triode region. As such, the NMOS switch 298 acts like a resistor. These bias levels are close to the trip point of the first inverter 220. Thus, in the high power mode, the sense amplifier 200 draws a considerable amount of current. The overall standby current is very high.
In the low power mode, the first input terminal 210 (Pd) and the fourth input terminal 299 (Pd_lat) normally stay HIGH and the second input terminal 294 (Pd_lat#) stays LOW. As a result, the biasing path 202 is OFF, isolating the third input terminal 296 (bitln) from the input sa_in 295 of the sense amplifier 200. When the biasing path 202 is disabled and the feed back latching path 280 is enabled, a latch is formed. Because each node is either at voltage supply Vcc or ground, the standby current in the low power mode is very low.
FIG. 3 shows a timing diagram of a plurality of control signals 300 operating the prior art sense amplifier of FIG. 1. Commencing in a latching phase 310, the signal Pd 110 is high and the conductive path to Vcc of pull-up PMOS transistor 112 is disabled. The signal Pd_lat 120 is high and Pd_lat# 115 is low. The signals Pd_lat 120 and Pd_lat# 115 in this condition will enable the latching path of the transmission gate 138, which connects sa_out 135 to sa_in 140, to make a latching condition. The low signal on Pd_lat# 115 applied to the gate of the first NMOS transistor 150, will isolate the memory cell array 165 from sa_in 140. In this latching phase 310, the latching path is enabled and the sense amplifier is disabled. This set of conditions defines the Low Power Mode.
When a memory location is to be read, a sensing phase 320 is entered. The sensing phase 320 is initiated by the word line 152 going to a high level for a memory cell 151 being selected, causing a sensing transition 340 to the sensing phase 320. The sensing transition 340 is defined by the input Pd 110 transitioning from high to low, the signal Pd_lat# 115 changing from low to high, and the signal Pd_lat 120 changing from high to low. Pd_lat 120 at a low level and Pd_lat# 115 at a high level will turn off the latching path from sa_out 135 to sa_in 140. Pd 110 being low will enable the pull-up PMOS transistor 112 to conduct and provide a bias to the sense amplifier input sa_in 140. A high level on Pd_lat# 115 is applied to the gate of the first NMOS transistor 150, making a coupling path from the memory cell array 165 to sa_in 140. The memory cell 151 selected is connected to the bit-line 170 through the activation of the select transistor 155. The contents of the selected memory cell are available to be coupled to the sense amplifier input sa_in 140 through the first NMOS transistor 150. In this phase, the latching path is disabled and the sense amplifier is enabled.
When the sensing phase 320 is concluded, a latching transition 345 is initiated by control logic (not shown). This transition is marked by the signal Pd 110 changing from low to high, the signal Pd_lat# 115 changing from high to low, and the signal Pd_lat 120 changing from low to high. In this phase the sense amplifier 100 is disabled and the latching path is active.
FIG. 3 also illustrates the timing diagram of these prior art control signals during a wake-up event 302. The sense amplifier 200 awakens by related signals that cause any separate word line 152 (FIG. 1) to change state. The change in state of these signals produces short pulses in the control signals. Graph 302 represents either input signals or feedback signals that change state from HIGH to LOW or vice versa. This causes the signal at the first input terminal 210 (Pd) to go LOW, creating a pulse 304. It also causes the signal at the second input terminal 294 (Pd_lat#) to become HIGH, representing pulse 306. Finally, the fourth signal 299 (Pd_lat) responds by having a pulse 308.
These pulses 304, 306, and 308 are about 20 ns in duration. During the short pulses, the first input terminal 210 (Pd) and the fourth input terminal 299 (Pd_lat) go LOW, and the fourth input signal 299 (Pd_lat#) goes HIGH. During these pulses, the sense amplifier 200 is enabled and the feedback latching path 280 is OFF. The sense amplifier 200 goes into the high power mode. That is, the sense amplifier 200 evaluates the possible new voltage levels created by the changes on input or feedback signals and responds to these changes. Once the pulse is over, the updated information is latched and stored until a next input or feedback transition.
During an initial sense phase 320, for a memory bit storing a logic high, a Vbias—HIGH voltage is present on the bit-line. After the sense amplifier switches to latch phase 310 after the wake up window expires, the bit-line node is isolated from the sa_in node. If we neglect the leakage current from the bit-line to ground, the bit-line holds the Vbias—HIGH voltage due to its electrical capacitance. The sa_in node is coupled to sa_out node because the formation of a latching connection during the latch phase 310. During the latch phase 310 a logic one, at a full CMOS level, is present at sa_in. In this case, a Vcc voltage level is present on sa_in. The second time the sense amplifier switches from latch phase 310 to sense phase 320 transistor 298 in FIG. 2 turns on since Pd_latch# goes to high during the sense phase 320. This couples sa_in and the bit-line together. At the onset of coupling, sa_in has a Vcc level stored on its associated parasitic capacitor 292. The bit-line node has a Vbias—HIGH level stored in its associated capacitance. Since Vcc usually is much higher than Vbias—HIGH, the charge in each capacitor redistributes to reach an equilibrium voltage. This process will conclude when there is no potential difference between these two nodes. The total amount of charge remains the same under the law of charge conservation. The final equilibrium voltage on the bit-line during the second sense high is higher than the original Vbias—HIGH voltage. In the subsequent latch phase 310, the higher voltage level is preserved on the bit-line, while sa_in is coupled back to Vcc due to the latching action. With a third sensing cycle, charge redistribution occurs again if the new bit-line voltage is lower than Vcc−VT; where VT is the threshold voltage of transistor 298. As a result, the bit-line goes to a level even higher voltage than the second time.
With regard to FIG. 4, continuing sensing phase events, pump the bit-line voltage even higher. If there are enough sensing cycles, the bit-line voltage level will eventually reach a saturated level at Vcc−VT. At this stage, even thought there is still a potential difference between sa_in and the bit-line node, the transistor 298 cannot be turned on to establish a conducting path to redistribute the charge. Because the third input terminal 296 (bitln) is pumped to a voltage level higher than a normal bit-line high bias voltage level, the following sensing logic low speed gets slowed down drastically. Normally, the voltage of bit-line path 290 only travels from about 100 mV to 200 mV to sense a logic LOW. Now it has to travel more than 2 volts to finally reach the voltage level for a sense amp to recognize a logic LOW. Because of the heavy loading on the bit-line path 290, it takes significantly more time to sense a logic LOW. This type of delay causes both functional failure and the failure to meet TPD specification.
What is needed is a circuit technique that reduces the effects of charge pumping events and achieves high-speed operation in the Low Power Mode.